The invention relates to an electronic device and fabrication method thereof, and more specifically to a package structure and fabrication method thereof.
A semiconductor chip such as an image chip is typically packaged by attachment to an area surrounded by a dam of a special chip carrier and formation of electrical connection between the chip and chip carrier, followed by encapsulation of the chip resulting from disposition of a glass sheet above the chip on the dam. The chip carrier with a dam is specially designed and manufactured for packaging an image chip, and the encapsulation structure includes the dam, glass sheet, a adhesive layer between the dam and glass sheet, and air between the chip and glass. This process is very complicated, has high production cost and low product reliability. Additionally, the interface between the dam and glass sheet may not be completely sealed, and thus destructive encapsulation testing is required, further increasing production cost and lowering throughput. Moreover, the chip may be exposed for a long time until disposition of the glass sheet, resulting in particle or other contaminations on the chip.
In a CSP (chip scale package) disclosed by SHELLCASE, a chip 601 with an image sensor 602 is laminated between a top glass sheet 650 and a bottom glass sheet 610 and completely encapsulated in epoxy 611 and 612 as shown in FIG. 6. This CSP has a simpler package structure, wiring thereof, however, is complicated as described in the following.
First, a wiring 604 is extended from a pad 603 of the chip 601 to an edge thereof, chip 601 and glass sheets 610, 650 are then laminated. When the chip 601 and bottom glass sheet 610 are cut or etched to divide the chip 601 from a wafer (not shown), exposing an end of the wiring 604, the wiring 604 is further extended along a sidewall of the chip 601 and bottom glass sheet 610 to a bottom surface thereof, followed by formation of solder bumps 614 on pads 613 thereon. The wiring extension is complicated and the wiring 604 may peel at the edge of chip 601 and at edges of the bottom surface of the bottom glass sheet 610, negatively affecting production cost and yield.